//------------------------------------------------------------------------- // S-100 Floppy Disk Controller Boot ROM //------------------------------------------------------------------------- // IO Map F0 (R) - Read Data from USART F0 (W) - Write Data to USART F1 (R) - 0 = ~Track0 1 = ~File Unsafe 2 = ~Ready 3 = ~Sector 4 = ~Index (Selected by IO select) 5 = Output state F1 (W) - Load transmit fill buffer F2 (R) - Read USART Status F2 (W) - Write sync byte buffer F3 (R) - Reset USART Receiver F3 (W) - 0 = Write current select 1 = File Unsafe 2 = Direction 3 = Write gate 4 = Step 5,6,7 - IO select 0 = Head Load 1 = J2-22 2 = J2-20 3 = J2-18 4 = J2-16 5 = J2-14 6 = J2-12 7 = J2-10 F4 (R) - Clear Receiver Data Available Wait F4 (W) - Clear Tramitter Bugger Empty Wait F5 (W) - Output trigger (Selected by IO select) F6 (W) - Output clear (Selected by IO select) // Copy ROM CF13-CFCC to RAM DF13-DFCC cf00 2113cf ld hl,0cf13h cf03 1113df ld de,0df13h cf06 06b9 ld b,0b9h cf08 7e ld a,(hl) cf09 12 ld (de),a cf0a 23 inc hl cf0b 13 inc de cf0c 05 dec b cf0d c208cf jp nz,0cf08h cf10 c313df jp 0df13h // Jump to code in RAM // This code is run from RAM df13 31cbdf ld sp,0dfcbh df16 af xor a df17 d3f3 out (0f3h),a // Clear drive control df19 d3f5 out (0f5h),a // Clear head load df1b dbf1 in a,(0f1h) // Check for ready df1d e604 and 04h df1f c213df jp nz,0df13h // Step the head 4 times in one direction then one back df22 cdacdf call 0dfach df25 cdacdf call 0dfach df28 cdacdf call 0dfach df2b cdacdf call 0dfach df2e cdb1df call 0dfb1h // Track zero? df31 dbf1 in a,(0f1h) df33 e601 and 01h df35 c22edf jp nz,0df2eh df38 dbff in a,(0ffh) // Read front panel switch df3a e601 and 01h df3c c4acdf call nz,0dfach // Step head to track 1 df3f d3f5 out (0f5h),a // Load head df41 3e81 ld a,81h // Set Sync byte to $81 df43 d3f2 out (0f2h),a // df45 f3 di // Disable interrupt df46 dbf1 in a,(0f1h) // Read drive input register df48 e610 and 10h // Wait for index df4a ca46df jp z,0df46h // df4d dbf1 in a,(0f1h) // Read drive input register df4f e610 and 10h // Wait for end of index df51 c24ddf jp nz,0df4dh // df54 dbf3 in a,(0f3h) // Reset UART recieve df56 dbf4 in a,(0f4h) // Wait for data df58 dbf0 in a,(0f0h) // Read data for UART df5a fe81 cp 81h // Repeat if it's not $81 df5c c23fdf jp nz,0df3fh // df5f dbf4 in a,(0f4h) // Wait for data df61 dbf0 in a,(0f0h) // Read low byte of buffer address df63 6f ld l,a // df64 dbf4 in a,(0f4h) // Wait for data df66 dbf0 in a,(0f0h) // Read high byte of buffer address df68 67 ld h,a // df69 e5 push hl // Push data onto stack df6a dbf4 in a,(0f4h) // Wait for data df6c dbf0 in a,(0f0h) // Read low byte of data length df6e 5f ld e,a // df6f dbf4 in a,(0f4h) // Wait for data df71 dbf0 in a,(0f0h) // Read high byte of data length df73 57 ld d,a // df74 d5 push de // Push data onto stack df75 dbf4 in a,(0f4h) // Wait for data df77 dbf0 in a,(0f0h) // Read data for UART df79 77 ld (hl),a // Write data to buffer df7a 23 inc hl // Increment buffer pointer df7b 1b dec de // Decrement length df7c 7a ld a,d // Check for end of data df7d b3 or e // df7e c275df jp nz,0df75h // Read next byte df81 dbf4 in a,(0f4h) // Read checksum low byte from UART df83 dbf0 in a,(0f0h) // df85 6f ld l,a // df86 dbf4 in a,(0f4h) // Read checksum high byte from UART df88 dbf0 in a,(0f0h) // df8a 67 ld h,a // df8b d1 pop de // Pop original data length from stack df8c c1 pop bc // Pop origianl data buffer address from stack df8d c5 push bc // Push data buffer address back on stack df8e e5 push hl // Push checksum back on stack df8f 210000 ld hl,0000h // df92 0a ld a,(bc) // Read first byte from buffer df93 85 add a,l df94 6f ld l,a df95 7c ld a,h df96 ce00 adc a,00h df98 67 ld h,a df99 03 inc bc df9a 1b dec de df9b 7a ld a,d df9c b3 or e df9d c292df jp nz,0df92h dfa0 d1 pop de // Pop expected checksum dfa1 7a ld a,d dfa2 94 sub h dfa3 c2a9df jp nz,0dfa9h dfa6 7b ld a,e dfa7 95 sub l dfa8 c8 ret z // Return checksum status dfa9 c313df jp 0df13h // Step the head dfac 3e14 ld a,14h dfae c3b3df jp 0dfb3h dfb1 3e10 ld a,10h // Step head dfb3 d3f3 out (0f3h),a // dfb5 e6ef and 0efh // Release step signal dfb7 d3f3 out (0f3h),a // dfb9 010004 ld bc,0400h // Wait for head to settle dfbc af xor a dfbd 0b dec bc dfbe b9 cp c dfbf c2bddf jp nz,0dfbdh dfc2 b8 cp b dfc3 c2bddf jp nz,0dfbdh dfc6 c9 ret // This data is copied to RAM but doesn't appear to be code dfc7 44 ld b,h dfc8 3044 jr nc,0d00eh dfca 3800 jr c,0cfcch dfcc 31 // The remainder of the ROM is probably data not code cfcd 3336 ld sp,3633h cfcf 3031 jr nc,0d002h cfd1 323133 ld (3331h),a cfd4 37 scf cfd5 44 ld b,h cfd6 39 add hl,sp cfd7 41 ld b,c cfd8 46 ld b,(hl) cfd9 44 ld b,h cfda 33 inc sp cfdb 46 ld b,(hl) cfdc 313341 ld sp,4133h cfdf 33 inc sp cfe0 324439 ld (3944h),a cfe3 46 ld b,(hl) cfe4 3630 ld (hl),30h cfe6 41 ld b,c cfe7 34 inc (hl) cfe8 39 add hl,sp cfe9 0d dec c cfea 0a ld a,(bc) cfeb 3a3130 ld a,(3031h) cfee 44 ld b,h cfef 37 scf cff0 3eca ld a,0cah cff2 d303 out (03h),a cff4 d305 out (05h),a cff6 3e27 ld a,27h cff8 d303 out (03h),a cffa d305 out (05h),a cffc c300cf jp 0cf00h cfff 33 inc sp